library ieee;
use ieee.std_logic_1164.all;

entity Counter4 is
        port (
                clk : in bit;
                hold_al : in bit; -- active low
                clr_al : in bit;
                overFlow : out bit;
                count : out bit_vector(5 downto 0)
        );
end entity Counter4;


architecture DATAFLOW of Counter4 is

        component TFlipFlop is 
        port (
                        clk, clr_al, t : in bit;
                        q : out bit
                
                );
        end component TFlipFlop;
        
        for all : TFlipFlop use entity work.TFlipFlop(dataflow);
        
        signal high : bit := '1';
        signal q_vec : bit_vector(5 downto 0);
        signal T1 : bit;
        signal T2 : bit;
        signal T3 : bit;
        signal T4 : bit;
        signal T5 : bit;
        
begin
    
        T1 <= q_vec(0) AND hold_al;
        T2 <= q_vec(1) AND q_vec(0) AND hold_al;
        T3 <= q_vec(2) AND q_vec(1) AND q_vec(0) AND hold_al;
        T4 <= q_vec(3) AND q_vec(2) AND q_vec(1) AND q_vec(0) AND hold_al;
        T5 <= q_vec(4) AND q_vec(3) AND q_vec(2) AND q_vec(1) AND q_vec(0) AND hold_al;

        T_1 : TFlipFlop port map(clk, clr_al, hold_al, q_vec(0));
        T_2 : TFlipFlop port map(clk, clr_al, T1, q_vec(1));
        T_3 : TFlipFlop port map(clk, clr_al, T2, q_vec(2));
        T_4 : TFlipFlop port map(clk, clr_al, T3, q_vec(3));
        T_5 : TFlipFlop port map(clk, clr_al, T4, q_vec(4));
        T_6 : TFlipFlop port map(clk, clr_al, T5, q_vec(5));
        
        count(5) <= q_vec(5);
        count(4) <= q_vec(4);
        count(3) <= q_vec(3);
        count(2) <= q_vec(2);
        count(1) <= q_vec(1);
        count(0) <= q_vec(0);
        overflow <= q_vec(5);

end architecture DATAFLOW;